M30222 Datasheet, PDF (138/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
UART2 in SPI mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The SPI functionality is an 8 bit, synchronous communication protocol that is user programmable to use
one of four different transfer formats. The four transfer formats support the four combinations of clock
phase and clock polarity, as the clock relates to the data. Figure 1.110 shows the SPI system level view.
The existing UART2 already provides two of the transfer formats, with the CKPOL control bit. The SPI
mode adds the ability to change the phase of the clock, with respect to the transmitted data, in each of
the two existing clock polarity formats.
Master MCU
MISO
MOSI
SPICLK
SSB
Slave MCU
MISO
MOSI
SPICLK
SSB
CSB
Fig. 1.110. SPI system level view
Slave MCU s SSB input may be tied to ground
if there is only one SPI slave in the system.
When operated in SPI mode the UART2 package pins provide the alternate SPI functions. MOSI,
Master Out Slave In, is multiplexed on pin P7[0]/TxD2. MOSI outputs data when UART2 is a SPI master
and inputs data when UART2 is a SPI slave. MISO, Master In Slave Out, is multiplexed on pin P7[1]/
RxD2. MISO inputs data when UART2 is a SPI master and outputs data when UART2 is a SPI slave.
SPICLK, SPI Clock, is multiplexed on pin P7[2]/CLK2. The SPI clock is input when the SPI is configured
as a slave or output when the SPI is configured as a master. SSB, Slave select input, is multiplexed on
pin P7[3]/RTSB/CTSB. This pin is used to select the active SPI slave.
The M30222 UART2 can be operated as an SPI master or as an SPI slave. Operation as an SPI Slave
or SPI Master is determined by the CKDIR contol bit. While in SPI mode, the TxD and RxD pins act as
the SPI MOSI and MISO pins. As implemented on the M30222, the SPI pins MOSI and MISO are open
drain.
There are two added control bits and one added status flag. Control bit SPIM is the SPI Mode enable,
which enables SPI operation. CPHA is the Clock Phase selection control bit. CPHA is used to chooses
the clock to data relationship. Combined with the existing CKPOL control bit, CPHA provides compat-
ibility with all four SPI transmission modes. CPHA is held at “0” when SPIM = “0”. The status flag
MDFLT is used to indicate that an SPI mode fault occurred.
Several existing configuration bits are required for SPI operation. SPI Slave / Master mode is controlled
by the existing CKDIR control bit. The UART is in SPI master mode when the clock is generated
internally and is in SPI slave mode when the clock is generated externally. CKPOL control bit select the
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