M30222 Datasheet, PDF (118/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Clock Synchronous Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.91). The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
CLK
IN
CLK
Note: This1 applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Fig. 1.91. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set
to "1", the unit is placed in continuous receive mode. When the receive buffer register is read, the unit
goes to a receive enable state without having to reset dummy data to the transmit buffer.
(e) Separate CTS/RTS pins function (UART0)
Refer to the Clock Asynchronous Serial I/O Mode section (Page 1-124) for setting the I/O pin functions.
This function is invalid if the transfer clock output from the multiple pin function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit 6 at address 037D16) = "1", the data are reversed when writing to the
transmit buffer register or reading from the receive buffer register. Figure 1.92 shows an example of the
serial data logic switch timing function.
•When LSB first
Transfer clock ^{“H”}
“L”
TxD2 “H”
(no reverse) _{“L”}
TxD2 ^{“H”}
(reverse) _{“L”}
Fig. 1.92. Serial data logic switch timing
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
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