M30222 Datasheet, PDF (141/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
UART2 in SPI mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Master Mode operation
SPI Master mode is entered by setting both SPI and CKDIR control bits to logic one. In master mode, the
UART will generate the clock to be driven on SPICLK. Transmitted data is shifted out on MOSI and and
receive data is shifted in on MISO.
The mode fault status flag, MDFLT, is set any time the state of the slave select pin, SS, is inconsistent with
an active SPI mode, SPIMSTR or SPISLV. Detection is intended to protect the MCU from damage due to
output driver contention.
A mode fault occurs if the SS pin of a slave SPI goes high during a transmissionor if the SS pin of a master
SPI goes low at any time A Mode Fault causes the following:
(1) The CLKDIR bit (in U2MR is forced to a “1”. This puts the UART into slave mode so that it is not driving
the CLK and MOSI pins.
(2) The UART is inhibited from driving it’s MISO pin.
(3) Mode Fault, MDF, status bit (bit 10 of U2RB) is set. A UART2 receiver interrupt is generated.
Mode Fault detection is disabled when the CTS2 /SSB function is not assigned to a port pin. In this case,
Slave Select is internally negated if the UART is configured for SPI Master operation.
A mode fault is cleared by setting the serial I/O mode bits (bits 2 through 0 of U2MR) to “000”. Also, the
Receiver Enable bit (RE2 of U2C1) must be cleared. When the Mode Fault is cleared, the UART will return to
master mode unless the CRS bit (in U2C0) is explicitly set.
Slave mode operation
SPI Slave mode is entered by setting the SPI control bit to logic one and the CKDIR control bit to logic zero.
Before transmission can start, the SSB pin of the slave SPI must be at logic zero.
When configured as a SPI slave, UART2 does not initiate any serial transfers. All transfers are initiated by an
external SPI bus master.
When the CPHA bit is a “1”, serial transfers begin with the falling edge of Slave Select. For CPHA = “0”,
serial transfers begin when the CLK leaves it’s idle state (the clock idle state is defined by the CKPOL bit in
U2C0). If the UART transmit buffer is empty when a serial transfer starts, the UART will drive the value “80”
hexadecimal on it’s MISO pin. The SPI should only write to the transmit buffer when it is empty. If the trans-
mit buffer is written during a serial transfer, the new data will be loaded into the transmit shifter at the end of
the current transfer.
The Slave Select function, SSB, is multiplexed on pin P7[3] along with CTSB. When UART2 is configured for
SPI operation, the SSB function must be selected by setting the U2C0 CRD bit to logic “0’ to enable CTS/RTS
functionality and additionally the U2C0 CRS bit must be set to logic “0” to enable CTS functionality. If the
CTS function is not both selected and enabled, the UART2 SPI logic will internally hold the SSB signal to the
appropriate level dependant on whether the SPI is configured for master or slave operation.
Slave select has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SSB pin is used to select a slave. For CPHA=0, SSB is also used to indicate the start of a trans-
mission. Since it is used to indicate the start of a transmission, SSB must be toggled high and low between
each byte transmitted for the CPHA=0 mode For CPHA=1 format, SSB may be kept asserted low between
transmitted bytes. If SSB is asserted while the SPI is configured as a master, a Mode Fault occurs.
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