M30222 Datasheet, PDF (139/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
UART2 in SPI mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
polarity of the transfer clock. The four different combinations of CKPOL and CPHA define the four
formats of the SPI communication protocols. While in SPI mode, the CRD control bit enables the CTS/
RTS pin to operate as SSB and CRS control bit selects CTS/RTS pin to operate as CTS/ SSB. Both
contorl bits must be properly configured to activate the SSB function. UFORM control bit selects the
UART transfer format, MSB or LSB. SPI data is transmitted MSB first.
SPI operation
Setting SMD[2:0]=010 in U2MR enables either SPI or IIC operation. Operation is undefined if both
IICM (U2SMR[0]) and SPI (U2SMR3[0]) control bits are set to logic one while SMD[2:0]=010.
Setting the SPIM control bit puts the UART2 into an SPI compatible mode. This mode is only valid in
the clock synchronous configuration and must not be entered when the UART2 is configured for
asynchronous operation. The internal / external clock select bit (CKDIR) in U2MR) determines
whether UART2 is an SPI master or slave. If internal clock is selected, the UART is an SPI master
and if external clock is selected, UART2 is an SPI slave. Figure 1.111 shows the signal wave forms.
Entering SPI mode has the following effects on operation:
(1) An alternate clock to data relationship can be chosen with the CPHA bit (in U2SMR3). This bit can only
be set when SPI bit is a “1”. All four SPI clock to data formats are possible by using the CPHA bit together
with the CKPOL bit (in U2C0). Figure 1.112 shows the function block diagram of SPI mode.
(2) The RxD pin becomes the MISO pin.
(3) The TxD pin becomes the MOSI pin.
(4) P7[3]/CTSB/RTSB functions as the Slave Select input. This input is active low.
(5) When configured as a master, a Mode Fault will be detected if the Slave Select input goes low. If no port
pin is assigned to be a slave select input, then mode fault detection is disabled.
SSB
SCLK
SCLK
SCLK
SCLK
CKPOL = 1
CPHA = 1
CKPOL = 1
CPHA = 0
CKPOL = 0
CPHA = 1
CKPOL = 0
CPHA = 0
MISO/MOSI
MSB
LSB
Fig. 1.111. SPI Transmission formats
NOTE: To prevent spurious clock transitions, configure the SPI modules as master or slave before enabling them. Enable the
master before enabling the slave. Disable the slave before disabling the master.
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