M30222 Datasheet, PDF (66/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following opera-
tions at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA
enable bit.
DMA request bit
The DMA request bit is set by a DMA transfer request signal. This signal is triggered by a factor selected
in advance by the DAMi Request Cause select bits.
DMA request factors include the following:
•Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
• External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi register.
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's
state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before
data transfer starts.
In addition, it can be set to "0" by use of a program, but cannot be set to "1".
There can be instances in which a change in DMA request factor selection bit causes the DMA request
bit to turn to "1". Be sure to set the DMA request bit to "0" after the DMA request factor selection bit is
changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
The timing of changes in the DMA request bit is explained below.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to
an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn
to "1" due to several factors. Turning the DMA request bit to "1" due to an internal factor is timed to be effected
immediately before the transfer starts.
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