M30222 Datasheet, PDF (23/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
M30222 Group
Rev. G
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
CM01
CM02
CM03
Bit name
Function
RW
Clock output function
select bits
b1 b0
0 0 : I/O port P75
0 1 : fC1 output
1 0 : f1 output
1 1 : Clock divide counter output
WAIT peripheral function 0 : Do not stop peripheral function clock in wait mode
clock stop bit
1 : Stop peripheral function clock in wait mode (Note 7)
Xcin-Xout drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
CM04
CM05
Port Xc Select Bit
Main clock (Xin -Xout )
stop bit (Note 3, 4)
0 : I/O port
1 : Xcin - Xcout generation
0 : Main clock on
1 : Main clock off
CM06 ^{Main clock division select 0 : CM16 and CM17 valid}
bit 0 (Note 6)
1 : Division by 8 mode
CM07
System clock select bit
(Note 5)
0 : Xin, Xout
1 : Xcin, Xcout
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: Changes to "1" when shifting to stop mode and at a reset.
Note 3: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 4: If this bit is set to "1", Xout turns "H". The built-in feedback resistor remains being connected, so X IN turns
pulled up to Xout ("H") via the feedback resistor.
Note 5: Set subclock (X_cin - X_cout) enable bit (CM04) to "1" and allow the subclock to stabilize before setting CM07 from
from "0" to "1". Do not write to both bits at the same time. Likewise, set the main clock stop bit (CM05) to "0" and
allow the subclock to stabilize before settng CM07 bit from "1" to "0".
Note 6: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 7: fC, fC132, fC1, fC32 is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
CM1
Address
000716
When reset
2016
Bit symbol
Bit name
CM10 All clock stop control bit
(Note 4)
Function
0 : Clock on
1 : All clocks off (stop mode)
RW
Reserved bit
Always set to "0"
CM14 ^{fC132 clock select bit}
0 : fC32
1 : fC1
CM15
CM16
CM17
Xin -Xout drive capacity
select bit (Note 2)
Main clock division
select bit 1 (Note 3)
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is
fixed at 8.
Note 4: If this bit is set to "1", Xout goes "H", and the built-in feedback resistor is cut off. Xcin and Xcout goes into high
impedance state.
Fig. 1.14. Clock control registers 0 and 1
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