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M30222 Datasheet, PDF (199/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions to Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the
device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check
function for use in standard serial I/O mode.
ROM code protect register
The ROM code protect function prevents reading out or modifying the contents of the flash memory during parallel
I/O mode. Figure 1.158 shows the ROM code protect control address (0FFFFF16). It is located at the hightest 8
bits of the 32 bit reset vector.
If one of the pair of ROM code protect bits is set to "0", ROM code protect is turned on, so that the contents of the
flash memory version are protected against readout and modification. ROM code protect is implemented
in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection
LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to "00", ROM code protect is turned off, so that the contents
of the flash memory version can be read out or modified. Once ROM code protect is tuned on, the contents of the
ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or some other mode to
rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol
ROMCP
Address
0FFFFF16
When reset
FF16
Bit symbol
Bit name
Reserved bit
ROMCP2
ROM code protect level
2 set bit (Note 1, 2)
Function
Always set this bit to "1"
b3 b2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
ROMCR ROM code protect reset
bit (Note 3)
ROMCP1 ROM code protect level
1 set bit (Note 1)
b5 b4
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LST tester, etc., is also inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, because these bits cannot be changed in paralell input/
output mode, they need to be rewritten in one of the two other modes.
Fig. 1.158. ROM code protect control addrsss
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