M30222 Datasheet, PDF (56/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
M30222 Group
Rev. G
Watchdog Timer
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
The Watchdog timer has the function of detecting when the program is out of control. The Watchdog timer
is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A
Watchdog timer interrupt is generated when an underflow occurs in the Watchdog timer. When XIN is
selected for the BCLK, bit 7 of the Watchdog timer control register (address 000F16) selects the prescaler
division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2
regardless of bit 7 of the Watchdog timer control register (address 000F16). Thus the Watchdog timer's
period can be calculated as given below. The Watchdog timer's period is, however, subject to an error due
to the prescaler.
With XIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (16 or 128) X Watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (2) X Watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the Watchdog timer's period becomes approximately 32.8 ms.
The Watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a Watchdog timer interrupt request is generated. The prescaler must be set before initializing the Watch-
dog timer. Once initialized, the Watchdog timer can only be stopped by a reset. The counter is reset to
7EEE16 by writing any value to the Watchdog timer start register (address 000E16). Figure 1.37 shows the
Watchdog timer block diagram. Figure 1.38 shows the Watchdog timer-related registers.
BCLK
HOLD
Write to the watchdog timer
start register
(address 000E16)
RESET
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
“CM07 = 0”
“WDC7 = 1”
1/128
“CM07 = 1”
1/2
Watchdog timer
Watchdog timer
interrupt request
Set to
“7FFF16”
Fig. 1.37. Block diagram of Watchdog timer
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