M30222 Datasheet, PDF (55/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

deUvnedloepr ^ment
Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Interrupt Precautions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
Figure 1.36. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the
interrupt is disabled. The program examples are described below:
Example 1:
INT_SWITCH1:
FCLR
AND.B
NOP
NOP
FSET
I
#00h, 0055h
I
:Disable interrupts.
;Clear TA0IC int. priority level and int. request bit.
;Four NOP instructions are required when using the HOLD function.
;Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
AND.B
MOV.W
FSET
I
#00h, 0055h
MEM, R0
I
:Disable interrupts.
;Clear TA0IC int. priority level and int. request bit.
;Dummy read.
;Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC
FCLR
AND.B
POPC
FLG
I
#00h, 0055h
FLG
;Push Flag register onto stack
;Diable interrupts.
;Clear TA0IC int. priority level and int. request bit.
;Enable interrupts.
The reason why two NOP instructions (four using the HOLD function) or dummy read is inserted before FSET I in
Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is
rewritten due to the effects of the instruction queue.
• When modifying an interrupt control register, it is recommended to use only the instructions: AND, OR,
BCLR, BSET. Using the "MOV" or other instruction may cause an interrrupt to be missed.
1-56