M30222 Datasheet, PDF (43/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Overview of Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum
required for the DIVX instruction (without wait).
Time (b) is as shown in Table 1.21.
Table 1.21. Time required for executing the interrupt sequence
Interrupt vector address
Even
Even
Odd (Note 2)
Odd (Note 2)
Stack pointer (SP) value
Even
Odd
Even
Odd
16-bit bus, without wait
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
8-bit bus, without wait
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt.
Add 1 cycle in the case of either an address coincidence interrupt or a single-step interrupt.
Note 2: If possible, locate an interrupt vector address in an even address.
Figure 1.25 shows the time required for executing the interrupt sequence
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
Internal
Address bus
Address 0000
Indeterminate
SP-2
SP-4
PC
Internal
Data bus
Interrupt
information
Indeterminate
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
SP-2 contents
Fig. 1.25. Time required for executing the interrupt sequence
SP-4 contents
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in
Table 1.22 is set in the IPL.
Table 1.22. Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Watchdog timer, NMI
RESET
Other
Value set in the IPL
7
0
No change
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