M30222 Datasheet, PDF (134/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
M30222 Group
Rev. G
UART2 in I²C Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I²C mode. Figure
1.107 shows the UART2 special mode register 2.
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I²C mode select bit 2.
Table 1.43 shows the types of control to be changed by I²C mode select bit 2 when the I²C mode
select bit is set to “1”. Figure 1.108 shows the timing characteristics of detecting the start condition
and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2)
to “1” in I²C mode.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Bit
symbol
Bit name
IICM2 I²C mode selection bit 2
Function
Refer to Table 1.43
CSC Clock-synchronous bit
SWC SCL wait output bit
ASL SDA output stop bit
STAC ^{UART2 initialization bit}
SWC2 SCL wait output bit 2
SDHI SDA output disable bit
SHTC Start/stop condition
control bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
Set this bit to "1" in I ²C mode
(refer to Figure 1.108)
Fig. 1.107. UART2 special mode register 2
RW
(Note)
Table 1.43. Functions changed by I²C mode select bit 2
Function
IICM2 = 0
IICM2 = 1
1 _{Factor of interrupt number 15}
No acknowledgment detection (NACK) UART2 transmission (the rising edge
of the final bit of the clock)
2 Factor of interrupt number 16
Acknowledgment detection (ACK)
UART2 reception (the falling edge
of the final bit of the clock)
3 _{DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK)}
is assigned to the DMA request
factor selection bits
UART2 reception (the falling edge of
the final bit of the clock)
4 Timing for transferring data from the The rising edge of the final bit of the
UART2 reception shift register to the reception clock
reception buffer.
The falling edge of the final bit of the
reception clock
5 ^{Timing for generating a UART2}
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
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