M30222 Datasheet, PDF (61/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BA16
When reset
0016
Bit symbol
Bit name
Function (Note)
DSEL0
DSEL1
DSEL2
DSEL3
DMA request cause
select bits
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3 (DMS=0) ^{/serial I/O3 (DMS=1)}
0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
RW
DMS
DMA request cause
expansion bit
0: Normal
1: DMA is caused by setting DSEL0 to DSEL3 (Expanded cause)
Software DMA
DSR
request bit
If software trigger is selected, a DMA request is generated by
setting this bit to “1” (When read, the value is always “0”)
Note: When the selected functions of the interrupt request are set, a DMA transfer request will occur.
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
XX000000 2
Bit symbol
Bit name
Function
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1) ^{0 : DMA not requested}
1 : DMA requested
DMAE
DSD
DAD
DMA enable bit
0 : Disabled
1 : Enabled
Source address direction _{0 : Fixed}
select bit (Note 3)
1 : Forward
Destination address
0 : Fixed
direction select bit (Note 3) _{1 : Forward}
RW
(Note 2)
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Fig. 1.41. DMAC register (2)
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