M30222 Datasheet, PDF (189/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program in ROM
Start
Single-chip mode or boot mode (Note 1)
Program in RAM
*1
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession) (Note 3)
Set processor mode register (Note 2)
Check CPU rewrite mode entry flag
Transfer CPU rewrite mode control
program to internal RAM
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
*1
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 4)
Write “0” to CPU rewrite mode select bit
End
Note 1: Apply 5V +/- 10% to CNVss pin by confirmation of CPU rewrite mode entry flag when starting operation
with single-chip mode.
Note 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio
select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716:
5 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state);
10 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state)
Note 3: For CPU rewrite mode sleect bit to be set to "1", the user needs to write a "0" and then a"1" to it in succession.
When not in this mode, it is not in "1". This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 4: Before exiting the CPU, rewrite mode after completing erase or program operation, always be sure to
execute a read array command to reset the flash memory.
Figure 1.151. CPU rewrite mode set/reset flowchart
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select
bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):
5.0 MHz or less when wait bit (bit 7 at address 000516) = 0 (no wait state)
10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (one wait state)
(2) Instruction inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of
the flash memory:
UND instruction, INTO instruction, JMPS instruction. JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode because they
refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table,
they can be used by transferring the vector into the RAM area.
(4) Reset
If the MCU is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal
operation. Set a 5 ms wait to release the reset operation. Also, when the reset has been released, the program
execute start address is automatically set to 07E00016, therefore program so that the execute start address of the
boot ROM is 07E00016.
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