M30222 Datasheet, PDF (59/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.23. DMAC specifications
Item
Number of channels
Transfer memory space
Maximum number of bytes transferred
DMA request factors (Note)
Channel priority
Transfer unit
Transfer address direction
Transfer mode
DMA interrupt request generation timing
Active
Inactive
Forward address pointer and reload timing
for transfer counter
Writing to register
Reading the register
Specification
2 (cycle-stealing method)
From any address in the 1m byte space to a fixed address
From a fixed address to any address in the 1 M byte space
From a fixed address to a fixed address
DMA-related registers (0020₁₆ to 003F₁₆) cannot be accessed
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
Falling edge of INT0 or INT1or both edges
(INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to Timer A4 interrupt requests
Timer B0 to Timer B5 interrupt requests
UART0 transfer and receive interrupt requests
UART1 transfer and receive interrupt requests
UART2 transfer and receive interrupt requests
Serial I/O 3,4 interrupt requests
A-D conversion interrupt requests
Software triggers
DMA0 has priority if DMA0 and DMA1 requests are generated simultaneously
8 bit or 16 bit
Forward/Fixed
(Forward direction cannot be specified for both source and destination
simultaneously)
Single transfer mode
After the transfer counter underflows, the DMA enable becomes 0 and the
DMAC becomes inactive.
Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter. The DMAC remains
active unless a 0 is written to the DMA enable bit.
When an underflow occurs in the transfer counter
When the DMA enable bit is set to 1 , the DMA is active.
When the DMA is active, data transfer starts each time the DMA transfer
request signal occurs.
When the DMA enable bit is set to 0 , the DMAC is inactive.
After the transfer counter underflows in single transfer mode.
When the DMAC is enabled, the DMA source pointer is loaded to the DMA forward
address pointer. The DMA transfer load pointer is copied to the DMA transfer
counter at that time.
Registers specified for forward direction transfer are always write enabled. Regis-
ters specified for fixed address transfer are write enabled when the DMA enable bit
is 0 .
Can be read anytime. However, when the DMA enable bit is 1 , reading the regis-
ter set up as the forward register is the same as reading the value of the forward
address pointer.
Note: DMA transfers do not effect any interrupt and are not affected by the interrupt enable flag (I flag) or by any interrupt
priority level.
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