M30222 Datasheet, PDF (39/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Overview of Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bits, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable
flag (I flag) and the IPL are located in the CPU flag register (FLG). Figure 1.23 shows the memory map
of the interrupt control registers.
Interrupt control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBiIC(i=3 to 5)
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 2)
TBiIC(i=0 to 2)
Address
0045 16 to 004716
004A16
004B16, 004C16
004D16
004E16
0051 16 005316, 004F16
0052 16, 005416, 005016
0055 16 to 005716
005A 16 to 005C16
When reset
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
XXXX0000 2
Bit symbol
ILVL0
Bit name
ILVL1
ILVL2
Interrupt priority level
select bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
(Note 2)
Note 1: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0 to 1)
INT2IC/SI3IC
INT31C/SI4IC
INT4IC/TA3IC
INT5/TA4IC
INTiIC(i= 6 to 7)
Bit symbol
Bit name
ILVL0
ILVL1
Interrupt priority level
select bit
ILVL2
IR
Interrupt request bit
POL
Polarity select bit
Reserved bit
Address
005D16 , 005E16
005F16
004416
005816
005916
004916, 004816
When reset
XX000000 2
XX000000 2
XX000000 2
XX000000 2
XX000000 2
XX000000 2
Function
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0: Selects falling edge
1: Selects rising edge
Always set to “0”
RW
(Note 2)
Nothing is assigned.
Write "0" when writing to these bits. If read, the value is "0".
Note 1 To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 2: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Figure 1.23. Memory map of the interrupt control registers.
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