M30222 Datasheet, PDF (188/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMCR
Address
03B416
When reset
XXXX0001 2
Bit symbol
Bit name
FMCR0 RY/BY status flag
Function
0: Busy (being written or erased)
1: Ready
RW
FMCR1
FMCR2
FMCR3
FMCR4
CPU rewrite mode
select bit (Note 1)
CPU rewrite mode
entry flag
Flash memory reset bit
(Note 2)
Write protect Bit
(Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
0: Normal mode
1: CPU rewrite mode
O
0: Normal operation
1: Reset
OO
0: Write protected
1: Write enabled
OO
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to 1, the user needs to write a "0" and then a "1" to it
in succession. Use the control program in RAM for write to this bit.
Note 2: For this bit to be set to "1", the user needs to write a "0" and then a
"1" to it in succession when the CPU rewrite mode selection bit is = "1".
Fig. 1.150 Flash memory control registers
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory.
During programming and erase operations, it is "0". Otherwise, it is "1".
Bit 1 is the CPU rewrite mode select bit. When this bit is set to "1", the M30222 accesses the CPU
rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode,
the CPU becomes unable to access the internal flash memory directly. Therefore, the control program
that sets this bit must be executed out of RAM. To set this bit to "1", it is necessary to write "0" and then
write "1" in succession. The bit can be set to "0" by only writing a "0".
Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode
has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit
is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU
rewrite mode select bit is "1" for this bit resets the control circuit. To release the reset, it is necessary
to set this bit to "0". If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so
that the flash memory can restore normal operation. Figure 1.151 shows a flowchart for setting/releas-
ing the CPU rewrite mode.
Bit 4 is the flash memory protect bit. The blocks are write protected when this bit is "0". The write
protect is disabled when the bit is "1". The MCU must be in CPU rewrite mode for this bit to have any
effect. To set this bit to "1", it is necessary to write "0" and then write "1" in succession.
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