M30222 Datasheet, PDF (123/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Clock Asynchronous Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example of transmit timing when tranfer data is 8 bits long (parity enabled, one-stop bit)
Tc
Transfer clock
Transmit enable ^{“1”}
bit(TE)
“0”
Transmit buffer
“1”
empty flag(TI)
“0”
TxD2
Data is set in UART2 transmit buffer register
Note
Transferred from UART2 transmit buffer register to UARTi transmit register
Start
bit
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Transmit register ^{“1”}
empty flag (TXEPT) _{“0”}
Transmit interrupt ^{“1”}
request bit (IR)
“0”
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f 1, f8, f32)
n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Fig. 1.95. Typical transmit timings in UART mode (UART2)
Example of receive timing when tranfer data is 8 bits long (parity disabled, one-stop bit)
BRGi count
source
.......
“1”
Receive enable bit
“0”
RxDi
Start bit
Sampled “L”
.......
D0
D1_.......D7
Receive data taken in
Stop bit
Transfer clock
Receive
complete flag
RTSi
Receive interrupt
request bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UARTi receive register to
UARTi receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Fig. 1.96. Typical receive timing in UART mode
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