M30222 Datasheet, PDF (131/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
M30222 Group
Rev. G
UART2 in I²C Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.105 shows the functional block diagram for I²C mode. Setting “1” in the I²C mode select bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock
input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission
output, so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7 at
address 037716) can be used to select between analog delay and digital delay. When digital delay is
selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2
special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.42.
P70 through P72 conforming to the simplified I ²C bus
P70/TxD2/SDA
P71/RxD2/SCL
P72/CLK2
Noise
Filter
Timer ^{SDDS = "0" or DL = "000"}
Selector
I/O
UART2
IICM=1
delay
Transmission
register
IICM=0
DQ
T Arbitration
UART2
Timer
IICM=1
IICM=0
Reception register
UART2
Start condition detection
Stop condition detection
S
R ^Q Bus busy
IICM=0
IICM=1
UART2 transmission/
NACK interrupt
request
IICM=0
IICM=1
UART2 reception/ACK
interrupt request
DMA1 request
Falling edge
detection
L-synchronous
output enabling bit
NACK
DQ
T
Noise
Filter
Noise
Filter
I/O R
Q
Data bus
(Port P71 output data latch)
Selector
UART2 Internal clock
IICM=1
CLK
IICM=1
External clock
IICM=0
UART2
DQ
T
9th pulse
ACK
IICM=1
Bus collision
detection
IICM=0
Bus collision/start, stop
condition detection
interrupt request
Port reading
UART2 IICM=0
Selector
I/O
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
Timer
To DMA0, DMA1
To DMA0
Fig. 1.105. Functional block diagram for I²C mode
Table 1.42. Delay circuit select conditions
Register value
IICM SDDS DL
Digital delay is selected
1
001
to
1 ₁₁₁
Analog delay is selected ¹
No delay
0
1 ₀₀₀
0 ₍₀₀₀₎
0 ₍₀₀₀₎
Contents
When digital delay is selected,no analog
delay is added. Only digital delay is effective
When DL is set ot "000", analog delay is
selected no matter what value is set in SDDS.
When SDDS is set to "0", DL is initialized, so
that DL = "000".
When IICM = "0", no delay circuit is selected.
Always made sure SDDS = "0".
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