M30222 Datasheet, PDF (63/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. Also,
the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination starts at odd ad-
dresses, there is one more source read cycle and destination write cycle than when the source and destina-
tion both start at even addresses.
(b) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased
for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.43 shows the transfer cycles for a source read. For convenience, the destination write cycle is
shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions
to both the destination write cycle and the source read cycle.
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