M30222 Datasheet, PDF (58/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. The DMAC shares the same data bus with the CPU. The DMAC uses
a high speed cycle-stealing method because it has a higher right to use the bus than the CPU. DMA
transfers word (16-bit) or a byte (8-bit) data. Figure 1.39 shows the block diagram of the DMAC. Table 1.23
shows the DMAC specifications. Figures 1.40 to 1.42 show the registers used by the DMAC.
Address bus
DMA0 transfer counter reload register TCR0 (16)
(addresses 0029 16, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
(addresses 0039 16, 003816)
DMA1 transfer counter TCR1 (16)
DMA0 source pointer SAR0(20)
(addresses 0022 16 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 0026 16 to 002416)
DMA0 forward address pointer (20) (Note)
DMA1 source pointer SAR1 (20)
(addresses 0032 16 to 003016)
DMA1 destination pointer DAR1 (20)
(addresses 0036 16 to 003416)
DMA1 forward address pointer (20) (Note)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.39. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA
transfer request signal. The DMA transfers are not affected by the interrupt enable flag (I flag) or by the
interrupt priority level and the DMA transfer doesn't affect any interrupt.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer
request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the
DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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