M30222 Datasheet, PDF (54/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Interrupt Precautions
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading address 0000016
• When a maskable interrupt occurs, the CPU reads the interrupt information (the interrupt number and
interrupt request level)from address 0000016 in the interrupt sequence.
The interrupt request bit of the interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software enables the highest priority interrupt source request bit.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The stack pointers immediately after reset are initialized to 000016. The stack pointers must nbe set to
valid RAM areas for proper operation. An interrupt occurring immediately after reset will cause a runaway
condition.
(3) The NMI interrupt
•The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused.
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
when the NMI interrupt is input.
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to the
NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is ignored.
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to the
NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this
instance, the CPU is returned to the normal state by a later interrupt.
• Minimum NMI pulse width is 1 BCLK cycle.
(4) External interrupts
• A minimum of 250ns pulse width is necessary for the signal input to pins INT0
through INT7 regardless of the CPU operation clock.
• When the polarity of the INT0 to INT7 pins is changed, the interrupt request bit is sometimes set to "1". After
changing the polarity, set the interrupt request bit to "0". Figure 1.36 shows the procedure for changing the
INT interrupt generate factor.
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