M30222 Datasheet, PDF (42/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

deUvnedloepr ^ment
Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Overview of Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
The interrupt sequence, described below, is performed over a period from the instant an interrupt is
accepted to the instant the interrupt routine is executed.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruc-
tion, the processor temporarily suspends the instruction being executed, and transfers control to the
interrupt sequence.
The processor carries out the following in sequence after an interrupt request:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
0000016.
(2) Saves the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63,
is executed).
(4) Saves the contents of the temporary register (Note) within the CPU in the stack area.
(5) Saves the contents of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first address
of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruc-
tion within the interrupt routine has been executed. This time comprises the period from the occurrence of an
interrupt to the completion of the instruction under execution at that moment (a) and the time required for
executing the interrupt sequence (b). Figure 1.24 shows the interrupt response time.
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Time
Instruction in
interrupt routine
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.24. Interrupt response time
1-43