M30222 Datasheet, PDF (130/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
Specifications in this manual are tentative and subject to change
M30222 Group
Rev. G
UART2 in I²C Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
0016
Bit
symbol
Bit name
IICM IIC mode selection bit
ABC
Arbitration lost detecting
flag control bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Normal mode
1 : IIC mode
Must always be “0”
0 : Update per bit
1 : Update per byte
Must always be “0”
RW
BBS Bus busy flag
0 : STOP condition detected Must always be “0”
1 : START condition detected
(Note 1)
LSYN SCLL sync output
enable bit
ABSCS ^{Bus collision detect}
sampling
clock select bit
0 : Disabled
1 : Enabled
Must always be “0”
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
SDDS
SDA digital delay select
bit (Note 2, 3)
0 : Analog delay output is
selected
Must always be "0"
1 : Digital delay output is
selected (Must always
be "0" when not using
I²C mode)
Note 1: Nothing but "0" may be written.
Note 2: When not in I ²C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this
bit - "0" , UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS
= "0", the U2SMR3 register cannot be read or written to.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected
only the digital delay value is effective.
UART2 Special mode register 3 (I²C and SPI bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
When reset
0016
Bit symbol
SPIM
CPHA
Bit name
SPI mode select bit
SPI clock-phase
select bit
Function during clock
synchronous serial I/O mode
0 : Normal mode
1 : SPI mode
0 : Data latched on
falling clock edge
1 : Data latched on
rising clock edge
Function during
UART mode
RW
Must always be "0'
Must always be "0'
Nothing is assigned. In an attempt to write to these bits, write "0". When read the
value is indeterminate. However, when SDDS = "1", a "0" value is read. (Note 1)
_
_
DL0
DL1
DL2
SDA digital delay
set up bit (Note
1, 2, 3, 4, 5)
b7 b6 b5
0 0 0 : Analog delay is selected
0 0 1 : 2 cycle of 1/f(X IN)
0 1 0 : 3 cycle of 1/f(X IN)
0 1 1 : 4 cycle of 1/f(X IN)
1 0 0 : 5 cycle of 1/f(X IN)
1 0 1 : 6 cycle of 1/f(X IN)
1 1 0 : 7 cycle of 1/f(X IN)
1 1 1 : 8 cycle of 1/f(X IN)
Digital delay
is selected
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
This bit can be read or written to when UART2 special mode register U2SMR at address 037716 bit 7
(SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3
(U2SMR3 is read after setting SDDS = "1", the value is "0016". When writing to U2SMR3 after setting
SDDS = "1", be sure to write 0s to bits 0 - 4. When SDDS = "0", This register cannot be written to;
when read, the value is indeterminate.
These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset
these bits are set to "000", with the analog delay circuit selected. However, because these bits can be read
only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate.
When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock,
the amount of delay increases by about 100ns. Be sure to take this into account when using this device.
Reset values for SPIM and CPHA are not affected by the state of SDDs. Their reset values are always "0".
Fig. 1.104. UART2 special mode register
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