M30222 Datasheet, PDF (120/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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in
this
manual
are
tentative
and
subject
to
MITSUBISHI
change
MICROCOMPUTERS
Rev. G
Clock Asynchronous Serial I/O Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.38. Specifications of UART Mode (2)
Item
Select function
Specification
• Separate CTS/RTS pins (UART0)
UART0 CTS and RTS functions each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function inverts logic value of transferring data. Start bit, parity bit
and stop bit are not inverted.
•TXD, RXD I/O polarity switch
This function inverts TXD port output and R XD port input. All I/O data
level is are inverted.
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
When reset
03A016, 03A816
0016
Bit symbol
Bit name
Function
SMD0
SMD1
SMD2
CKDIR
STPS
PRY
PRYE
Serial I/O mode select bit
Internal / external clock
select bit
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Internal clock
1 : External clock (Note)
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
0 : Sleep mode deselected
1 : Sleep mode selected
Note: Set the corresponding port direction register to "0".
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
RW
Bit symbol
SMD0
SMD1
SMD2
CKDIR
STPS
Bit name
Serial I/O mode select bit
Internal / external clock
select bit
Stop bit length select bit
PRY
Odd / even parity
select bit
PRYE
Parity enable bit
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
Note: Usually set to “0”.
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Must always be fixed to “0”
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Fig. 1.93. UARTi transmit/receive mode register in UART mode
RW
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