M30222 Datasheet, PDF (145/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Serial I/O (3, 4)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions for setting an SOUTi initial value
When using an external clock for the tranfer clock, the SOUTi pin output level during a non-transfer
time can be set to the high or the low state. Figure 1.115 shows the timing chart for setting an SOUTi
initial value.
(Example) With "H" selected for SOUTi:
Signal written to the S I/Oi
transmission/reception
register
SOUTi's initial value
set bit (SMi7)
S I/Oi port select bit
(SMi3)
D0
SOUTi (internal)
Port output
D0
SOUTi terminal output
Initial value = "H" (Note)
(i = 3, 4)
Setting the SOUTi Port selection
initial value to H (normal port SOUTi)
Note: The set value is output only when the external clock has been selected. When
initializing SOUTi, make sure the CLKi pin input is held "H" level.
If the internal clock has been selected or if SOUT output disable has been set,
this output goes to the high-impedance state.
Fig. 1.115. Timing chart for setting SOUTi's initial value
S I/Oi operation timing
Figure 1.116 shows the S I/Oi operation timing.
S I/Oi port select bit SMi3 = 0
SOUTi initial value select bit
SMi7 = 1
(SOUTi: Internal "H" level)
S I/Oi port select bit
SMi3 = 0 1
(Port select: Normal port SOUTi)
SOUTi terminal = "H" output
Signal written to the S I/Oi register
="L" "H" "L"
(Falling edge)
SOUTi terminal = Outputting
stored data in the S I/Oi transmission/
reception register
"H"
SI/Oi internal clock _"L"
Transfer clock ^"H"
(Note 1) ^"L"
Signal written to the ^"H"
S I/Oi register ^"L"
S I/Oi output SOUTi "H"
(i= 3, 4)
"L"
S I/Oi input SINi ^"H"
(i= 3, 4)
"L"
SI/Oi interrupt ^"1"
request bit (i= 3, 4) "0"
1.5 cycle (max)
Hiz
D0
D1
D2
D3
D4
D5
D6
Note 2
Hiz
D7
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register.
(i=3,4) (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the S OUTi pin becomes to the high-impedance state after the transfer finishes.
Fig. 1.116. S I/Oi operation timing chart
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