M30222 Datasheet, PDF (67/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Direct Memory Access Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on
which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these
pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with
the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer
starts similarly to the state in which an internal factor is selected.
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn
to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When
DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access,
then DMA1 starts data transfer and gives the bus right to the CPU.
Figure 1.44 shows an example in which DMA transfer is carried out in minimum cycles at the time when DMA
transfer request signals due to external factors concurrently occur.
Example of DMA transmission that is carried out in minimum cycles
at the time DMA transmission occur concurrently.
BCLK
DMA0
///////////
DMA1
///////////
CPU _{/////////////////}
///////
//////////////
INT0
DMA0
request bit
INT1
DMA1
request bit
Bus
control
Fig. 1.44. An example of DMA transfer affected by external factors
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