M30222 Datasheet, PDF (46/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Overview of Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag
register (FLG) as it was immediately before the start of interrupt sequence and the contents of the
program counter (PC), both of which have been saved in the stack area. Then control returns to the
program that was being executed before the acceptance of the interrupt request, so that the sus-
pended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (check-
ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bits. If the same interrupt priority level is assigned, however, the interrupt assigned a
higher hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control is
distributed to the interrupt routine. Figure 1.28 shows the priorities of hardware interrupts.
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.28. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 1.29 shows the circuit that judges the interrupt priority level.
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