M30222 Datasheet, PDF (24/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Clock output
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
The M30222 provides for a clock output signal (P73/CLKOUT pin) of user defined frequency. The clock
output function select bit (CM00, CM01) allows you to choose the clock source from f1, fC1, or a divide-by-
n clock for output to the P73/CLKOUT pin. The clock divide counter is an 8-bit counter whose count source
is f32, and its divide ratio can be set in the range of 0016 to FF16. Also, the clock divided counter can be
controlled for start or stop by the clock divide counter start flag. Figure 1.15 shows a block diagram of
clock output. Figure 1.16 shows a clock divided counter related register.
P75
f1
fC1
Clock source
selection
P75/CLKOUT
1/2
f32
Clock divided counter (8)
Division n+1 n=0016 to FF16
Reload register (8)
Address 036E16
Low-order 8 bits
Data bus low-order bits
Example:
When f(XIN)=10MHz, count source = f32
n=0716 : approx. 19.5kHz
n=2616 : approx. 4.0kHz
n=4D16 : approx. 2.0kHz
n=9B16 : approx. 1.0kHz
Fig. 1.15. Block diagram of clock output
Clock divided counter
b7
b0
Symbol
CDC
Address
036E16
8-bit timer
Function
When reset
XX16
Values that can be set
0016 to FF16
RW
Clock divided counter control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CDCC
Address
036C16
When reset
0XXXXXXX 2
Bit symbol
Bit name
Function
Nothing is assigned. Write "0" when writing to these bits.
When read, the value is indeterminate.
CDCS
Clock divided counter
start flg
0 : Stop
1 : Start
Fig. 1.16. Clock divided counter related register
1-25
RW