PIC24FJ128GC010 Datasheet, PDF (98/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 7-1: RCON: RESET CONTROL REGISTER
R/W-0
R/W-0
U-0
R/W-0
U-0
TRAPR⁽¹⁾ IOPUWR⁽¹⁾
—
RETEN⁽²⁾
—
bit 15
R/W-0
DPSLP⁽¹⁾
R/W-0
EXTR⁽¹⁾
bit 7
R/W-0
SWR⁽¹⁾
R/W-0
SWDTEN⁽⁴⁾
R/W-0
WDTO⁽¹⁾
R/W-0
SLEEP⁽¹⁾
R/W-0
IDLE⁽¹⁾
R/W-0
CM⁽¹⁾
R/W-1
BOR⁽¹⁾
R/W-0
PMSLP⁽³⁾
bit 8
R/W-1
POR⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
TRAPR: Trap Reset Flag bit⁽¹⁾
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit⁽¹⁾
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an
Address Pointer and caused a Reset
0 = An illegal opcode or Uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
RETEN: Retention Mode Enable bit⁽²⁾
1 = Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core)
0 = Retention mode is disabled; normal voltage levels are present
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Flag bit⁽¹⁾
1 = Device has been in Deep Sleep mode
0 = Device has not been in Deep Sleep mode
CM: Configuration Word Mismatch Reset Flag bit⁽¹⁾
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
PMSLP: Program Memory Power During Sleep bit⁽³⁾
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep
EXTR: External Reset (MCLR) Pin bit⁽¹⁾
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit⁽¹⁾
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
Note 1:
2:
3:
4:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN
bit has no effect.
Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from
occurring.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS30009312B-page 98
 2012-2013 Microchip Technology Inc.