PIC24FJ128GC010 Datasheet, PDF (463/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
I
I/O Ports
Analog Port Pins Configuration (ANSx) .................... 184
Analog/Digital Function of an I/O Pin ........................ 184
Input Change Notification (ICN) ................................ 191
Input Voltage Levels for Port/Pin
Tolerated Description Input............................... 185
Open-Drain Configuration ......................................... 184
Parallel (PIO) ............................................................ 183
Peripheral Pin Select ................................................ 192
Pull-ups and Pull-Downs........................................... 191
Selectable Input Sources .......................................... 193
Selectable Output Sources ....................................... 194
I²C
Clock Rates............................................................... 251
Communicating as Master in Single
Master Environment.......................................... 249
Reserved Addresses................................................. 251
Setting Baud Rate as Bus Master............................. 251
Slave Address Masking ............................................ 251
Input Capture
32-Bit Cascaded Mode ............................................. 224
Operations ................................................................ 224
Synchronous and Trigger Modes.............................. 223
Input Capture with Dedicated Timers................................ 223
Instruction Set
Overview ................................................................... 419
Summary................................................................... 417
Symbols Used in Opcode Descriptions..................... 418
Interfacing Program and Data Spaces ................................ 78
Inter-Integrated Circuit. See I²C.
Internal Band Gap References ......................................... 341
Internet Address................................................................ 467
Interrupt Controller ............................................................ 103
Interrupt Vector Table (IVT) .............................................. 103
Interrupts
Control and Status Registers .................................... 107
Implemented Vectors ................................................ 105
Reset Sequence ....................................................... 103
Setup and Service Procedures ................................. 158
Trap Vectors ............................................................. 104
Vector Table.............................................................. 104
J
JTAG Interface .................................................................. 412
K
Key Features..................................................................... 399
L
LCD Controller .................................................................... 14
Liquid Crystal Display (LCD) Controller ............................ 315
Low-Voltage/Retention Regulator ..................................... 173
M
Memory Organization.......................................................... 45
Microchip Internet Web Site .............................................. 467
Modulator. See Data Signal Modulator.
MPLAB ASM30 Assembler, Linker, Librarian ................... 414
MPLAB Integrated Development
Environment Software............................................... 413
MPLAB PM3 Device Programmer .................................... 415
MPLAB REAL ICE In-Circuit Emulator System................. 415
MPLINK Object Linker/MPLIB Object Librarian ................ 414
N
Near Data Space ................................................................ 48
O
On-Chip Voltage Regulator............................................... 409
POR.......................................................................... 409
Standby Mode .......................................................... 409
Oscillator Configuration
Clock Switching ........................................................ 165
Sequence ......................................................... 165
Configuration Bit Values for Clock Selection ............ 160
FRC Self-Tuning....................................................... 166
Initial Configuration on POR ..................................... 160
USB Operation ......................................................... 167
Special Considerations..................................... 168
Output Compare
32-Bit Cascaded Mode ............................................. 227
Operations ................................................................ 228
Synchronous and Trigger Modes ............................. 227
Output Compare with Dedicated Timers........................... 227
P
Packaging ......................................................................... 447
Details....................................................................... 449
Marking..................................................................... 447
Peripheral Pin Select (PPS).............................................. 192
Available Peripherals and Pins................................. 192
Configuration Control................................................ 195
Considerations for Use ............................................. 196
Input Mapping........................................................... 193
Mapping Exceptions ................................................. 195
Output Mapping ........................................................ 194
Peripheral Priority ..................................................... 192
Registers .................................................................. 197
Pin Descriptions
100-Pin Devices ........................................................... 6
121-Pin Devices (BGA) ................................................ 9
64-Pin Devices ............................................................. 4
Pinout Descriptions....................................................... 19–31
Power-Saving Features .................................................... 171
Clock Frequency and Clock Switching ..................... 181
Doze Mode ............................................................... 181
Hardware-Based Modes........................................... 173
Instruction-Based Modes.......................................... 172
Deep Sleep....................................................... 174
I/O Pins..................................................... 175
Retention Mode ........................................ 174
Idle.................................................................... 173
Sleep ................................................................ 173
Low-Voltage/Retention Sleep................... 173
Power-on Resets (PORs) ......................................... 176
Selective Peripheral Control ..................................... 181
Vbat Mode ................................................................ 177
I/O Pins............................................................. 177
With no RTCC .................................................. 177
Product Identification System ........................................... 469
Program Memory
Access Using Table Instructions ................................ 80
Address Construction ................................................. 78
Address Space ........................................................... 45
Flash Configuration Words ......................................... 46
Hard Memory Vectors................................................. 46
Memory Maps............................................................. 45
Organization ............................................................... 46
Reading From Program Memory Using EDS ............. 81
 2012-2013 Microchip Technology Inc.
DS30009312B-page 463