PIC24FJ128GC010 Datasheet, PDF(172/472 Page) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

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PIC24FJ128GC010 Datasheet, PDF (172/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

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PIC24FJ128GC010 FAMILY

TABLE 10-2: EXITING POWER SAVING MODES

Mode

Interrupts

All

INT0

Exit Conditions

Code

All

Resets

RTCC

POR MCLR Alarm

WDT

VDD

Restore(2)

Execution

Resumes

Idle

Y

Y

Y

Y

Y

Y

Y

N/A Next instruction

Sleep (all modes) Y

Y

Y

Y

Y

Y

Y

N/A

Deep Sleep

N

Y

N

Y

Y

Y

Y(1)

N/A Reset vector

Retention Deep

N

Y

N

Y

Y

Y

Y(1)

N/A Next instruction

Sleep

VBAT

N

N

N

N

N

N

N

Y

Reset vector

Note 1: Deep Sleep WDT.

2: A POR or POR-like Reset results whenever VDD is removed and restored in any mode except for

Retention Deep Sleep.

10.1.1

INSTRUCTION-BASED

POWER-SAVING MODES

Three of the power-saving modes are entered through

the execution of the PWRSAV instruction. Sleep mode

stops clock operation and halts all code execution. Idle

mode halts the CPU and code execution, but allows

peripheral modules to continue operation. Deep Sleep

mode stops clock operation, code execution and all

peripherals, except RTCC and DSWDT. It also freezes

I/O states and removes power to Flash memory, and

may remove power to SRAM.

The assembly syntax of the PWRSAV instruction is shown

in Example 10-1. Sleep and Idle modes are entered

directly with a single assembler command. Deep Sleep

requires an additional sequence to unlock and enable

the entry into Deep Sleep, which is described in

Section 10.4.2 âEntering Deep Sleep Modeâ.

Note:

SLEEP_MODE and IDLE_MODE are

constants defined in the assembler

include file for the selected device.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

âwake-upâ.

The features enabled with the low-voltage/retention

regulator result in some changes to the way that Sleep

and Deep Sleep modes behave. See Section 10.3

âSleep Modeâ and Section 10.4 âDeep Sleep Modeâ

for additional information.

10.1.1.1 Interrupts Coincident with Power

Save Instructions

Any interrupt that coincides with the execution of a

PWRSAV instruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

For Deep Sleep mode, interrupts that coincide with the

execution of the PWRSAV instruction may be lost. If the

low-voltage/retention regulator is not enabled, the

microcontroller resets on leaving Deep Sleep and the

interrupt will be lost. If the low-voltage/retention regula-

tor is enabled, the microcontroller will exit Deep Sleep

and the interrupt will then be handled.

Interrupts that occur during the Deep Sleep unlock

sequence will interrupt the mandatory five-instruction

cycle sequence timing and cause a failure to enter

Deep Sleep. For this reason, it is recommended to

disable all interrupts during the Deep Sleep unlock

sequence.

EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX

// Syntax to enter Sleep mode:

PWRSAV

#SLEEP_MODE

; Put the device into SLEEP mode

//

//Synatx to enter Idle mode:

PWRSAV

#IDLE_MODE

; Put the device into IDLE mode

//

// Syntax to enter Deep Sleep mode:

// First use the unlock sequence to set the DSEN bit (see Example 10-2)

BSET

DSCON, #DSEN

;Enable Deep Sleep

BSET

DSCON, #DSEN

; Enable Deep Sleep(repeat the command)

PWRSAV

#SLEEP_MODE

; Put the device into Deep SLEEP mode

DS30009312B-page 172

ï£ 2012-2013 Microchip Technology Inc.

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