PIC24FJ128GC010 Datasheet, PDF (174/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
10.4 Deep Sleep Mode
Deep Sleep mode provides the lowest levels of power
consumption available from the Instruction-Based
modes. PIC24FJ128GC010 family devices have two
Deep Sleep modes: Legacy Deep Sleep, found in other
PIC24F devices, and Retention Deep Sleep, described
below.
Deep Sleep modes have these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Deep
Sleep mode if the WDT, or RTCC with LPRC as
the clock source, is enabled.
• The dedicated Deep Sleep WDT and BOR
systems, if enabled, are used.
• The RTCC and its clock source continue to run, if
enabled. All other peripherals are disabled.
Entry into Deep Sleep mode is completely under
software control. Exit from the Deep Sleep modes can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (if the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
10.4.1 RETENTION DEEP SLEEP
Unlike Deep Sleep mode, Retention Deep Sleep mode
represents an incremental increase in power consump-
tion. Although it also allows the device to operate at a
VCORE of 1.2V, the low-voltage/retention regulator is
used in this mode to maintain the contents of the data
RAM, which slightly increases current consumption.
Maintaining data RAM (including the SFRs) has sev-
eral effects that make Retention Deep Sleep different
form Deep Sleep:
• The wake-up sources are the same as those for
Deep Sleep mode.
• Wake-up from Retention Deep Sleep allows the
device to resume its previous state and start code
execution where it left off, instead of restarting at
the Reset vector (as with Deep Sleep).
10.4.2 ENTERING DEEP SLEEP MODE
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register and then executing a Sleep
command (PWRSAV #SLEEP_MODE) within one instruc-
tion cycle to minimize the chance that Deep Sleep will
be spuriously entered. If the low-voltage/retention
regulator is already enabled, prior to setting the DSEN
bit, the device will enter Retention Deep Sleep.
If the PWRSAV command is not given within one
instruction cycle, the DSEN bit will be cleared by the
hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
automatically cleared when exiting Deep Sleep mode.
Note:
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
The sequence to enter Deep Sleep mode is:
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.4.6 “Deep Sleep WDT”.
2. If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (CW4<6>).
3. If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module. For more information on RTCC,
see Section 23.0 “Real-Time Clock and
Calendar (RTCC)”.
4. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
5. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
Note:
A repeat sequence is required to set the
DSEN bit. The repeat sequence (repeating
the instruction twice) is required to write to
any of the Deep Sleep registers (DSCON,
DSWAKE, DSGPR0, DSGPR1). This is
required to prevent the user from entering
Deep Sleep by mistake. Any write to these
registers has to be done twice to actually
complete the write (see Example 10-2).
6. Enter Deep Sleep mode by issuing 3 NOP
commands and then a PWRSAV #0 instruction.
DS30009312B-page 174
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