PIC24FJ128GC010 Datasheet, PDF (402/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 34-2: CW2: FLASH CONFIGURATION WORD 2
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
IESO
bit 15
R/PO-1
VBTBOR
R/PO-1
R/PO-1
R/PO-1
R/PO-1
WDTCMX ALTCVREF⁽¹⁾ ALTADREF⁽¹⁾ FNOSC2
R/PO-1
FNOSC1
R/PO-1
FNOSC0
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
r-0
R/PO-1
R/PO-1
FCKSM1 FCKSM0 OSCIOFCN WDTCLK1 WDTCLK0
r
POSCMD1 POSCMD0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
PO = Program Once bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7-6
Unimplemented: Read as ‘1’
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
VBTBOR: VBAT BOR Enable bit
1 = VBAT BOR is enabled
0 = VBAT BOR is disabled
WDTCMX: WDT Clock Multiplex Control bit
1 = Enables WDT clock multiplexing
0 = Disables clock multiplexing
ALTCVREF: External CVREF+/CVREF- Location Select bit⁽¹⁾
1 = CVREF+/CVREF- are mapped to RA9/RA10, respectively
0 = CVREF+/CVREF- are mapped to RB0/RB1, respectively
ALTADREF: External AVREF+/AVREF- Location Select bit⁽¹⁾
1 = AVREF+/AVREF- are mapped to RA9/RA10, respectively
0 = AVREF+/AVREF- are mapped to RB0/RB1, respectively
FNOSC<2:0>: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1:
2:
These bits should be treated as reserved on the 64-pin devices (PIC24FJ64GC006 and
PIC24FJ128GC006) and should always be programmed to ‘0’. The AVREF+/CVREF+ and AVREF-/CVREF-
functions are located on RB0 and RB1 on these devices.
The 31 kHz FRC source is used when a Windowed WDT mode is selected and the LPRC is not being
used as the system clock. The LPRC is used when the device is in Sleep mode and in all other cases.
DS30009312B-page 402
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