PIC24FJ128GC010 Datasheet, PDF (372/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 27-2: SD1CON2: S/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
CHOP1
CHOP0
SDINT1
SDINT0
—
bit 15
U-0
R/W-0
R/W-0
—
SDWM1
SDWM0
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
HS/C-0
—
—
—
RNDRES1 RNDRES0
—
—
SDRDY
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-12
bit 11-10
bit 9-8
bit 7-5
bit 4-3
bit 2-1
bit 0
CHOP<1:0>: Chopping Enable bits
11 = Chopping is enabled (recommended setting, improves result quality)
10 = Reserved
01 = Reserved
00 = Chopping is disabled
SDINT<1:0>: S/D Interrupt Event Generation Select bits
11 = Interrupt on every sample clock
10 = Interrupt on every fifth sample clock
01 = Interrupt when New Result < Old Result
00 = Interrupt when New Result > Old Result
Unimplemented: Read as ‘0’
SDWM<1:0>: S/D Output Result Register Write bits
11 = Reserved; do not use
10 = SD1RESH/SD1RESL is never updated (used for threshold compare operations)
01 = SD1RESH/SD1RESL is updated on every interrupt
00 = SD1RESH/SD1RESL is updated on every interrupt when SDRDY = 0
Unimplemented: Read as ‘0’
RNDRES<1:0>: Round Data Control bits
11 = Round result to 8 bits
10 = Round result to 16 bits
01 = Round result to 24 bits
00 = No Rounding
Unimplemented: Read as ‘0’
SDRDY: S/D Filter Data Ready bit (set by hardware)
1 = Sync filter delay is satisfied (clear this bit in software)
0 = Sync filter delay is not satisfied yet
DS30009312B-page 372
 2012-2013 Microchip Technology Inc.