PIC24FJ128GC010 Datasheet, PDF (69/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

TABLE 4-29: PARALLEL MASTER/SLAVE PORT REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMCON1 0600 PMPEN
—
PSIDL ADRMUX1 ADRMUX0 —
MODE1
PMCON2 0602 BUSY
—
ERROR TIMEOUT
—
—
—
PMCON3 0604 PTWREN PTRDEN PTBE1EN PTBE0EN
—
AWAITM1 AWAITM0
PMCON4 0606 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9
PMCS1CF 0608 CSDIS CSP CSPTEN BEP
—
WRSP RDSP
PMCS1BS 060A BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17
PMCS1MD 060C ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0
—
—
PMCS2CF 060E CSDIS CSP CSPTEN BEP
—
WRSP RDSP
PMCS2BS 0610 BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17
PMCS2MD 0612 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0
—
—
PMDOUT1 0614
Data Out Register 1<15:8>
PMDOUT2 0616
Data Out Register 2<15:8>
PMDIN1 0618
Data In Register 1<15:8>
PMDIN2 061A
Data In Register 2<15:8>
PMSTAT 061C IBF
IBOV
—
—
IB3F
IB2F
IB1F
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
MODE0 CSF1
CSF0
ALP ALMODE
— BUSKEEP IRQM1 IRQM0
— RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16
AWAITE
—
PTEN22 PTEN21 PTEN20 PTEN19 PTEN18 PTEN17 PTEN16
PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0
SM
ACKP PTSZ1 PTSZ0
—
—
—
—
—
BASE16 BASE15
—
—
—
—
—
—
—
—
DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0
SM
ACKP PTSZ1 PTSZ0
—
—
—
—
—
BASE16 BASE15
—
—
—
—
—
—
—
—
DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0
Data Out Register 1<7:0>
Data Out Register 2<7:0>
Data In Register 1<7:0>
Data In Register 2<7:0>
IB0F
OBE
OBUF
—
—
OB3E OB2E OB1E OB0E
0000
0000
0000
0000
0000
0200
0000
0000
0600
0000
xxxx
xxxx
xxxx
xxxx
008F
TABLE 4-30: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP
File Name Addr Bit 15 Bit 14
Bit 13
Bit 12
Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
ALRMVAL 0620
Alarm Value Register Window Based on ALRMPTR<1:0>
ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5
RTCVAL 0624
RTCC Value Register Window Based on RTCPTR<1:0>
RCFGCAL 0626 RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5
RTCPWC 0628 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0 —
—
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The status of the RCFGCAL and RTCPWR registers on POR is ‘0000’, and on other Resets, it is unchanged
Bit 4
ARPT4
CAL4
—
Bit 3
ARPT3
CAL3
—
Bit 2
ARPT2
CAL2
—
Bit 1
Bit 0
All
Resets
xxxx
ARPT1 ARPT0 0000
CAL1
—
CAL0
—
xxxx
Note 1
Note 1
TABLE 4-31: DATA SIGNAL MODULATOR (DSM) REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
MDCON
062A MDEN
—
MDSIDL
—
—
—
MDSRC
062C
—
—
—
—
—
—
MDCAR
062E CHODIS CHPOL CHSYNC —
CH3
CH2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
—
—
CH1
Bit 8
—
—
CH0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
SODIS
CLODIS
MDOE
—
CLPOL
MDSLR MDOPOL
—
—
CLSYNC —
—
MS3
CL3
Bit 2
—
MS2
CL2
Bit 1
—
MS1
CL1
Bit 0
MDBIT
MS0
CL0
All
Resets
0020
000x
0000