PIC24FJ128GC010 Datasheet, PDF (101/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
7.1 Special Function Register Reset
States
Most of the Special Function Registers (SFRs) associ-
ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSCx bits in Flash Configuration
Word 2 (CW2) (see Table 7-2). The RCFGCAL and
NVMCON registers are only affected by a POR.
7.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the System Reset
signal, SYSRST, is released after the POR delay time
expires.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the
system clock source after the SYSRST signal is
released.
7.3 Brown-out Reset (BOR)
PIC24FJ128GC010 family devices implement a BOR
circuit that provides the user with several configuration
and power-saving options. The BOR is controlled by
the BOREN (CW3<12>) Configuration bit.
When BOR is enabled, any drop of VDD below the BOR
threshold results in a device BOR. Threshold levels are
described in Section 37.1 “DC Characteristics”
(Parameter DC17B).
7.4 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the Oscillator Configuration bits.
Refer to the “PIC24F Family Reference Manual”,
Section 6.0 “Oscillator” (DS39700) for further details.
TABLE 7-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC<2:0> Configuration bits
(CW2<10:8>)
COSC<2:0> Control bits
(OSCCON<14:12>)
 2012-2013 Microchip Technology Inc.
DS30009312B-page 101