PIC24FJ128GC010 Datasheet, PDF (108/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 8-1:
U-0
—
bit 15
SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
IPL2^(2,3)
bit 7
R/W-0
IPL1^(2,3)
R/W-0
IPL0^(2,3)
R-0
RA⁽¹⁾
R/W-0
N⁽¹⁾
U-0
—
R/W-0
OV⁽¹⁾
U-0
—
R/W-0
Z⁽¹⁾
R/W-0
DC⁽¹⁾
bit 8
R/W-0
C⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 7-5
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
2:
3:
See Register 3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
The IPLx bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level.
The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
DS30009312B-page 108
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