PIC24FJ128GC010 Datasheet, PDF (173/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
10.1.2
HARDWARE-BASED
POWER-SAVING MODE
The hardware-based VBAT mode does not require any
action by the user during code development. Instead, it
is a hardware design feature that allows the micro-
controller to retain critical data (using the DSGPRx
registers) and maintain the RTCC when VDD is removed
from the application. This is accomplished by supplying
a backup power source to a specific power pin. VBAT
mode is described in more detail in Section 10.5 “Vbat
Mode”.
10.1.3
LOW-VOLTAGE/RETENTION
REGULATOR
PIC24FJ128GC010 family devices incorporate a
second on-chip voltage regulator, designed to provide
power to select microcontroller features at 1.2V, nomi-
nal. This regulator allows features, such as data RAM
and the WDT, to be maintained in power-saving modes
where they would otherwise be inactive, or maintain
them at a lower power than would otherwise be the
case.
The low-voltage/retention regulator is only available
when Sleep or Deep Sleep modes are invoked. It is
controlled by the LPCFG Configuration bit (CW1<10>)
and in firmware by the RETEN bit (RCON<12>).
LPCFG must be programmed (= 0) and the RETEN bit
must be set (= 1) for the regulator to be enabled.
10.2 Idle Mode
Idle mode provides these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.8
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the Interrupt Service
Routine (ISR).
10.3 Sleep Mode
Sleep mode includes these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT or RTCC, with LPRC as the
clock source, is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items, such as the Input Change Notification
(ICN) on the I/O ports, or peripherals that use an
external clock input. Any peripheral that requires
the system clock source for its operation will be
disabled in Sleep mode.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
10.3.1
LOW-VOLTAGE/RETENTION SLEEP
MODE
Low-Voltage/Retention Sleep mode functions as Sleep
mode with the same features and wake-up triggers.
The difference is that the low-voltage/retention regula-
tor allows Core Digital Logic Voltage (VCORE) to drop to
1.2V nominal. This permits an incremental reduction of
power consumption over what would be required if
VCORE was maintained at a 1.8V (minimum) level.
Low-Voltage Sleep mode requires a longer wake-up
time than Sleep mode, due to the additional time
required to bring VCORE back to 1.8V (known as TREG).
In addition, the use of the low-voltage/retention regula-
tor limits the amount of current that can be sourced to
any active peripherals, such as the RTCC/LCD, etc.
 2012-2013 Microchip Technology Inc.
DS30009312B-page 173