PIC24FJ128GC010 Datasheet, PDF (298/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
19.7.3
USB ENDPOINT MANAGEMENT
REGISTERS
REGISTER 19-21: U1EPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LSPD⁽¹⁾ RETRYDIS⁽¹⁾
—
EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)⁽¹⁾
1 = Direct connection to a low-speed device is enabled
0 = Direct connection to a low-speed device is disabled
RETRYDIS: Retry Disable bit (U1EP0 only)⁽¹⁾
1 = Retry NAK transactions are disabled
0 = Retry NAK transactions are enabled; retry is done in hardware
Unimplemented: Read as ‘0’
EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN and EPRXEN = 1:
1 = Disables Endpoint n from control transfers; only TX and RX transfers are allowed
0 = Enables Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
For All Other Combinations of EPTXEN and EPRXEN:
This bit is ignored.
EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled
EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled
EPSTALL: Endpoint STALL Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake is enabled
0 = Endpoint handshake is disabled (typically used for isochronous endpoints)
Note 1: These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits
are always unimplemented and read as ‘0’.
DS30009312B-page 298
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