PIC24FJ128GC010 Datasheet, PDF (351/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 26-2: ADCON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
U-0
R/W-0
U-0
PVCFG1
PVCFG0
—
NVCFG0
—
bit 15
R/W-0
BUFORG
R/W-1
r
R/W-1
r
bit 8
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
r
r
—
—
—
—
REFPUMP⁽¹⁾
r
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7-6
bit 5-2
bit 1
bit 0
PVCFG<1:0>: Converter Voltage Reference Configuration for ADREF+ bits
10 = BGBUF1 Internal Reference⁽²⁾
01 = External VREF+
00 = AVDD
Unimplemented: Read as ‘0’
NVCFG0: Converter Voltage Reference Configuration for ADREF- bit
1 = External VREF-
0 = AVSS
Unimplemented: Read as ‘0’
BUFORG: ADRES Result Buffer Organization Control bit
1 = Result buffer is organized as an indexed buffer; ADTBLn conversion result is stored in ADRESn
(where n is the same number between 0-31)
0 = Result buffer is organized as a 32 result deep FIFO like buffer; results get stored in the sequential
order that they are generated
Reserved: Always write ‘11’ to these bits for normal A/D operation
Reserved: Always write ‘00’ to these bits for normal A/D operation
Unimplemented: Read as ‘0’
REFPUMP: A/D Reference Charge Pump Control bit⁽¹⁾
1 = Reference charge pump is enabled, to optimize internal operation with small references < (0.65 * AVDD)
0 = Reference charge pump is disabled
Reserved: Always write ‘0’ to this bit for normal A/D operation
Note 1:
2:
Never set the REFPUMP bit unless the magnitude of the A/D reference (ex: AVREF+ – AVREF-) is less than
(0.65 * AVDD).
In order to use the BGBUF1 internal reference for the A/D, firmware must also configure and enable the
buffer through the BUFCON1.
 2012-2013 Microchip Technology Inc.
DS30009312B-page 351