PIC24FJ128GC010 Datasheet, PDF (166/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
A recommended code sequence for a clock switch
includes the following:
1. Disable interrupts during the OSCCON register
unlock and write sequence.
2. Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back instructions.
3. Write the new oscillator source to the NOSCx
bits in the instruction immediately following the
unlock sequence.
4. Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
5. Set the OSWEN bit in the instruction immediately
following the unlock sequence.
6. Continue to execute code that is not clock-sensitive
(optional).
7. Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
the failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 9-1.
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
#OSCCONH, w1
MOV
#0x78, w2
MOV
#0x9A, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Set new oscillator selection
MOV.b
WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
MOV
#OSCCONL, w1
MOV
#0x46, w2
MOV
#0x57, w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Start oscillator switch operation
BSET
OSCCON,#0
9.5 FRC Active Clock Tuning
PIC24FJ128GC010 family devices include an automatic
mechanism to calibrate the FRC during run time. This
system uses active clock tuning from a source of known
accuracy to maintain the FRC within a very narrow
margin of its nominal 8 MHz frequency. This allows for a
frequency accuracy that is well within the requirements
of the “USB 2.0 Specification”, regarding full-speed USB
devices.
Note:
The self-tune feature maintains sufficient
accuracy for operation in USB Device
mode. For applications that function as a
USB host, a high-accuracy clock source
(±0.05%) is still required.
The self-tune system is controlled by the bits in the
upper half of the OSCTUN register. Setting the STEN
bit (OSCTUN<15>) enables the self-tuning feature,
allowing the hardware to calibrate to a source selected
by the STSRC bit (OSCTUN<12>). When STSRC = 1,
the system uses the Start-of-Frame (SOF) packets
from an external USB host for its source. When
STSRC = 0, the system uses the crystal-controlled
SOSC for its calibration source. Regardless of the
source, the system uses the TUN<5:0> bits
(OSCTUN<5:0>) to change the FRC Oscillator’s fre-
quency. Frequency monitoring and adjustment is
dynamic, occurring continuously during run time. While
the system is active, the TUNx bits cannot be written to
by software.
Note:
To use the USB as a reference clock
tuning source (STSRC = 1), the micro-
controller must be configured for USB
device operation and connected to a
non-suspended USB host or hub port.
If the SOSC is to be used as the reference
clock tuning source (STSRC = 0), the
SOSC must also be enabled for clock
tuning to occur.
The self-tune system can generate a hardware
interrupt, FSTIF. The interrupt can result from a drift of
the FRC from the reference by greater than 0.2% in
either direction, or whenever the frequency deviation is
beyond the ability of the TUNx bits to correct (i.e.,
greater than 1.5%). The STLOCK and STOR status bits
(OSCTUN<11,9>) are used to indicate these
conditions.
The STLPOL and STORPOL bits (OSCTUN<10,8>)
configure the FSTIF interrupt to occur in the presence
or the absence of the conditions. It is the user’s respon-
sibility to monitor both the STLOCK and STOR bits to
determine the exact cause of the interrupt.
Note:
The STLPOL and STORPOL bits should
be ignored when the self-tune system is
disabled (STEN = 0).
DS30009312B-page 166
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