PIC24FJ128GC010 Datasheet, PDF (178/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER⁽¹⁾
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
DSEN
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 7
r-0
R/W-0
R/C-0, HS
r
DSBOR⁽²⁾ RELEASE
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit r = Reserved bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-3
bit 2
bit 1
bit 0
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
DSBOR: Deep Sleep BOR Event bit⁽²⁾
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Releases I/O pins from their state previous to Deep Sleep entry, and allows their respective TRISx
and LATx bits to control their states
Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms the POR.
DS30009312B-page 178
 2012-2013 Microchip Technology Inc.