PIC24FJ128GC010 Datasheet, PDF (176/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance and pins
configured as outputs continue to drive their previous
value. After waking up, the TRIS and LAT registers, and
the SOSCEN bit (OSCCON<1>), are reset. If firmware
modifies any of these bits or registers, the I/O will not
immediately go to the newly configured states. Once
the firmware clears the RELEASE bit (DSCON<0>),
the I/O pins are “released”. This causes the I/O pins to
take the states configured by their respective TRISx
and LATx bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
10.4.6 DEEP SLEEP WDT
To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (CW4<7>). The
device WDT need not be enabled for the DSWDT to
function. Entry into Deep Sleep modes automatically
resets the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (CW4<5>). The posts-
caler options are programmed by the DSWDPS<4:0>
Configuration bits (CW4<4:0>). The minimum time-out
period that can be achieved is 1 ms and the maximum is
25.7 days. For more details on DSWDT configuration
options, refer to Section 34.0 “Special Features”.
10.4.6.1 Switching Clocks in Deep Sleep
Mode
Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC, of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from the
SOSC clock source. The RTCC clock source is selected
with the RTCLK<1:0> bits (RTCPWC<11:10>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled) without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.
10.4.7
CHECKING AND CLEARING THE
STATUS OF DEEP SLEEP
Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this
case, the Reset was due to some event other
than a Deep Sleep mode exit.
• The DPSLP bit is clear, but the POR bit is set; this
is a normal POR.
• Both the DPSLP and POR bits are set. This
means that Deep Sleep mode was entered, the
device was powered down and Deep Sleep mode
was exited.
10.4.8 POWER-ON RESETS (PORs)
VDD voltage is monitored to produce PORs. Since
exiting from Deep Sleep mode functionally looks like a
POR, the technique described in Section 10.4.7
“Checking and Clearing the Status of Deep Sleep”
should be used to distinguish between Deep Sleep and
a true POR event. When a true POR occurs, the entire
device, including all Deep Sleep logic (Deep Sleep
registers, RTCC, DSWDT, etc.), is reset.
DS30009312B-page 176
 2012-2013 Microchip Technology Inc.