PIC24FJ128GC010 Datasheet, PDF (466/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
U1OTGIE (USB OTG Interrupt Enable,
Host Mode) ....................................................... 292
U1OTGIR (USB OTG Interrupt Status,
Host Mode) ....................................................... 291
U1OTGSTAT (USB OTG Status, Host Mode) .......... 281
U1PWRC (USB Power Control) ................................ 283
U1SOF (USB OTG Start-of-Token Threshold,
Host Mode) ....................................................... 288
U1STAT (USB Status) .............................................. 284
U1TOK (USB Token, Host Mode) ............................. 287
UxMODE (UARTx Mode) .......................................... 260
UxSTA (UARTx Status and Control) ......................... 262
WKDYHR (RTCC Weekday and Hours Value) ......... 330
YEAR (RTCC Year Value) ........................................ 329
Resets
BOR (Brown-out Reset) .............................................. 97
Brown-out Reset (BOR) ............................................ 101
Clock Source Selection ............................................. 101
CM (Configuration Mismatch Reset) ........................... 97
Delay Times .............................................................. 102
Device Times ............................................................ 101
IOPUWR (Illegal Opcode Reset) ................................ 97
MCLR (Pin Reset) ....................................................... 97
POR (Power-on Reset) ............................................... 97
RCON Flags, Operation ............................................ 100
SFR States................................................................ 101
SWR (RESET Instruction)........................................... 97
TRAPR (Trap Conflict Reset)...................................... 97
UWR (Uninitialized W Register Reset)........................ 97
WDT (Watchdog Timer Reset).................................... 97
Revision History ................................................................ 459
RTCC
Alarm Configuration .................................................. 333
Alarm Mask Settings (figure)..................................... 334
Calibration ................................................................. 333
Clock Source Selection ............................................. 324
Power Control ........................................................... 334
Register Mapping ...................................................... 324
Source Clock............................................................. 323
VBAT OPERATION........................................................ 334
Write Lock ................................................................. 324
S
Secondary Oscillator Operation ........................................ 168
Serial Peripheral Interface (SPI) ....................................... 237
Serial Peripheral Interface. See SPI.
SFR Space.......................................................................... 48
Sigma-Delta A/D
Differences Compared to Conventional A/Ds ........... 370
Sigma-Delta A/D Converter
Required Connections ................................................ 38
Software Simulator (MPLAB SIM)..................................... 415
Software Stack .................................................................... 77
Special Features ................................................................. 15
SPI .................................................................................... 237
T
Timer1............................................................................... 215
Timer2/3 and Timer4/5 ..................................................... 217
Timing Diagrams
12-Bit A/D DNL ......................................................... 443
12-Bit A/D INL........................................................... 443
16-Bit S/D A/D DNL .................................................. 446
16-Bit S/D A/D INL.................................................... 446
CLKO and I/O Timing ............................................... 440
External Clock........................................................... 438
Triple Comparator............................................................. 381
Triple Comparator Module ................................................ 381
U
UART ................................................................................ 257
UARTx
Baud Rate Generator (BRG) .................................... 258
Infrared Support........................................................ 259
Operation of UxCTS and UxRTS Pins...................... 259
Receiving
8-Bit or 9-Bit Data Mode ................................... 259
Transmitting
8-Bit Data Mode................................................ 259
9-Bit Data Mode................................................ 259
Break and Sync Sequence ............................... 259
Universal Asynchronous Receiver Transmitter. See UART.
Universal Serial Bus
Interrupts
and USB Transactions...................................... 275
Universal Serial Bus. See USB OTG.
Unused I/Os........................................................................ 38
USB On-The-Go (OTG) ...................................................... 14
USB OTG.......................................................................... 265
Buffer Descriptors
Assignment in Different Buffering Modes ......... 271
Buffer Descriptors and BDT...................................... 270
Device Mode Operation ............................................ 275
DMA Interface........................................................... 271
Hardware
Calculating
Transceiver Power Requirements ............ 269
Hardware Configuration............................................ 267
Device Mode..................................................... 267
External Interface ............................................. 269
Host and OTG Modes....................................... 268
VBUS Voltage Generation ................................. 269
Host Mode Operation................................................ 276
Interrupts .................................................................. 274
Operation .................................................................. 278
HNP .................................................................. 279
SRP .................................................................. 278
Registers .................................................................. 280
VBUS Voltage Generation ......................................... 269
W
Watchdog Timer (WDT).................................................... 410
Control Register........................................................ 410
Windowed Operation ................................................ 410
WWW Address ................................................................. 467
WWW, On-Line Support ..................................................... 12
DS30009312B-page 466
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