PIC24FJ128GC010 Datasheet, PDF (56/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

TABLE 4-10: UART REGISTER MAPS
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
U1MODE 0220 UARTEN
—
USIDL IREN RTSMD
—
U1STA
0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
U1TXREG 0224
—
—
—
—
—
—
U1RXREG 0226
—
—
—
—
—
—
U1BRG
0228
U2MODE 0230 UARTEN
—
USIDL IREN RTSMD
—
U2STA
0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
U2TXREG 0234
—
—
—
—
—
—
U2RXREG 0236
—
—
—
—
—
—
U2BRG
0238
U3MODE 0250 UARTEN
—
USIDL IREN RTSMD
—
U3STA
0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
U3TXREG 0254
—
—
—
—
—
—
U3RXREG 0256
—
—
—
—
—
—
U3BRG
0258
U4MODE 02B0 UARTEN
—
USIDL IREN RTSMD
—
U4STA
02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
U4TXREG 02B4
—
—
—
—
—
—
U4RXREG 02B6
—
—
—
—
—
—
U4BRG
02B8
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH
UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
—
Transmit Register
—
Receive Register
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH
UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
—
Transmit Register
—
Receive Register
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH
UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
—
Transmit Register
—
Receive Register
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH
UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR
—
Transmit Register
—
Receive Register
Baud Rate Generator Prescaler Register
Bit 2
Bit 1
Bit 0
All
Resets
PDSEL1 PDSEL0 STSEL 0000
FERR OERR URXDA 0110
xxxx
0000
PDSEL1 PDSEL0 STSEL
FERR OERR URXDA
0000
0000
0110
xxxx
0000
PDSEL1 PDSEL0 STSEL
FERR OERR URXDA
0000
0000
0110
xxxx
0000
PDSEL1 PDSEL0 STSEL
FERR OERR URXDA
0000
0000
0110
xxxx
0000
0000
TABLE 4-11: SPI REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
SPI1STAT 0240 SPIEN
—
SPISIDL
—
— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV
SPI1CON1 0242
—
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN
CKP
SPI1CON2 0244 FRMEN SPIFSD SPIFPOL —
—
—
—
—
—
—
SPI1BUF 0248
Transmit and Receive Buffer
SPI2STAT 0260 SPIEN
—
SPISIDL
—
— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV
SPI2CON1 0262
—
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN
CKP
SPI2CON2 0264 FRMEN SPIFSD SPIFPOL —
—
—
—
—
—
—
SPI2BUF 0268
Transmit and Receive Buffer
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SRXMPT
MSTEN
—
SRXMPT
MSTEN
—
SISEL2
SPRE2
—
SISEL2
SPRE2
—
Bit 3
SISEL1
SPRE1
—
SISEL1
SPRE1
—
Bit 2
SISEL0
SPRE0
—
SISEL0
SPRE0
—
Bit 1
SPITBF
PPRE1
SPIFE
SPITBF
PPRE1
SPIFE
Bit 0
All
Resets
SPIRBF
PPRE0
SPIBEN
0000
0000
0000
SPIRBF
PPRE0
SPIBEN
0000
0000
0000
0000
0000