PIC24FJ128GC010 Datasheet, PDF (74/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
4.2.5 EXTENDED DATA SPACE (EDS)
The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range. EDS includes any additional internal data mem-
ory not directly accessible by the lower 32-Kbyte data
address space and any external memory through the
Enhanced Parallel Master Port (EPMP).
In addition, EDS also allows read access to the
program memory space. This feature is called Program
Space Visibility (PSV) and is discussed in detail in
Section 4.3.3 “Reading Data from Program Memory
Using EDS”.
Figure 4-4 displays the entire EDS space. The EDS is
organized as pages, called EDS pages, with one page
equal to the size of the EDS window (32 Kbytes). A par-
ticular EDS page is selected through the Data Space
Read register (DSRPAG) or Data Space Write register
(DSWPAG). For PSV, only the DSRPAG register is
used. The combination of the DSRPAG register value
and the 16-bit wide data address forms a 24-bit
Effective Address (EA).
FIGURE 4-4:
EXTENDED DATA SPACE
Special
Function
Registers
0000h
0800h
Internal
Data
Memory
Space
(up to
30 Kbytes)
8000h
008000h
FF8000h
The data addressing range of PIC24FJ128GC010 family
devices depends on the version of the Enhanced
Parallel Master Port (EPMP) implemented on a particu-
lar device; this is, in turn, is a function of the device pin
count. Table 4-40 lists the total memory accessible by
each of the devices in this family. For more details on
accessing external memory using EPMP, refer to the
“PIC24F Family Reference Manual”, Section 42.
“Enhanced Parallel Master Port (EPMP)” (DS39730).
.
TABLE 4-40: TOTAL ACCESSIBLE DATA
MEMORY
Family
Internal
RAM
External RAM
Access Using
EPMP
PIC24FJXXXGC010
PIC24FJXXXGC006
8K
Up to 16 Mbytes
8K
Up to 64K
Note:
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations,
0800h to 7FFFh, in the lower Data Space).
EDS Pages
000000h
7F8000h
000001h
7F8001h
32-Kbyte
EDS
Window
External
Memory
Access
Using
EPMP⁽¹⁾
External
Memory
Access
Using
EPMP⁽¹⁾
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Upper
Word)
Program
Space
Access
(Upper
Word)
FFFEh
00FFFEh
DSxPAG
= 001h
FFFFFEh
DSx PAG
= 1FFh
EPMP Memory Space⁽¹⁾
007FFEh
DSRPAG
= 200h
7FFFFEh
DSRPAG
= 2FFh
007FFFh
DSRPAG
= 300h
Program Memory
7FFFFFh
DSRPAG
= 3FFh
Note 1: The range of addressable memory available is dependent on the device pin count and EPMP implementation.
DS30009312B-page 74
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