PIC24FJ128GC010 Datasheet, PDF (381/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
30.0 TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
the “PIC24F Family Reference Manual”,
“Scalable Comparator Module”
(DS39734). The information in this data
sheet supersedes the information in the
FRM.
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and VREF+) and a
voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG, VBG/2, VBG/6 and CVREF).
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 30-1. Diagrams of the possible individual
comparator configurations are shown in Figure 30-2.
Each comparator has its own control register,
CMxCON (Register 30-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 30-2).
FIGURE 30-1:
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
CCH<1:0>
CXINB
CXINC
CXIND
VBG
VBG/2
CVREF+
Input
Select
Logic
00
01
10
11
00
01
11
CVREFM<1:0>⁽¹⁾
VIN-
VIN+ ^C1
VIN-
VIN+ ^C2
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C1OUT
COUT ^Pin
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C2OUT
COUT ^Pin
CXINA
CVREF+
CVREF
CVREFP⁽¹⁾
CREF
0
+
1
1
0
VIN-
VIN+ ^C3
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C3OUT
COUT ^Pin
Note 1: Refer to the CVRCON register (Register 31-1) for bit details.
 2012-2013 Microchip Technology Inc.
DS30009312B-page 381