PIC24FJ128GC010 Datasheet, PDF (373/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 27-3: SD1CON3: S/D CONTROL REGISTER 3
R/W-0
SDDIV2⁽¹⁾
bit 15
R/W-0
SDDIV1⁽¹⁾
R/W-0
SDDIV0⁽¹⁾
R/W-0
SDOSR2
R/W-0
SDOSR1
R/W-0
SDOSR0
R/W-0
SDCS1
R/W-0
SDCS0
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
SDCH2
SDCH1
SDCH0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-10
bit 9-8
bit 7-3
bit 2-0
SDDIV<2:0>: S/D Input Clock Divider/Postscaler Ratio bits⁽¹⁾
111 = Reserved
110 = 64
101 = 32
100 = 16
011 = 8
010 = 4
001 = 2
000 = 1 (No divider, clock selected by SDCS<1:0> provided directly to A/D)
SDOSR<2:0>: S/D Oversampling Ratio (OSR) Selection bits
111 = Reserved
110 = 16 (fastest result, lowest quality)
101 = 32
100 = 64
011 = 128
010 = 256
001 = 512
000 = 1024 (slowest result, best quality)
SDCS<1:0>: S/D A/D Module Clock Source Select bits
11 = Reserved
10 = Primary Oscillator (OSCI/CLKI)
01 = FRC (8 MHz)⁽²⁾
00 = System clock (FOSC/2)
Unimplemented: Read as ‘0’
SDCH<2:0>: S/D Analog Channel Input Select bits (positive input/negative input)
1xx = Reserved
011 = Measures the reference selected by SDREFP/SDREFN (used for gain error measurements)
010 = CH1SE/SVSS (single-ended measurement of CH1SE)
001 = CH1+/CH1- (Differential Channel 1)
000 = CH0+/CH0- (Differential Channel 0)
Note 1:
2:
To avoid overclocking or underclocking the module, set SDDIV<2:0> to obtain an A/D clock frequency
(input frequency selected by SDCS<1:0> source, divided by selected SDDIVx ratio) at or between 1 MHz
and 4 MHz.
8 MHz FRC output is used directly, prior to the FRCDIV postscaler.
 2012-2013 Microchip Technology Inc.
DS30009312B-page 373