PIC24FJ128GC010 Datasheet, PDF (167/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
9.6 Oscillator Modes and USB
Operation
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled and not in a suspended
operating state. Since this is well beyond the maximum
CPU clock speed, a method is provided to internally
generate both the USB and system clocks from a single
oscillator source. PIC24FJ128GC010 family devices
use the same clock structure as most other PIC24FJ
devices, but include a two-branch PLL system to
generate the two clock signals.
The USB PLL block is shown in Figure 9-2. In this
system, the input from the Primary Oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip, 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed, divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed,
divide-by-3 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIV<1:0> bits select the system
clock speed; available clock options are listed in
Table 9-2.
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must man-
ually configure the PLL divider to generate the required
4 MHz output, using the PLLDIV<3:0> Configuration
bits. This limits the choices for Primary Oscillator
frequency to a total of 8 possibilities, shown in
Table 9-3.
TABLE 9-2: SYSTEM CLOCK OPTIONS
DURING USB OPERATION
MCU Clock Division
(CPDIV<1:0>)
Microcontroller
Clock Frequency
Note
None (00)
32 MHz
2 (01)
16 MHz
4 (10)⁽¹⁾
8 MHz
8 (11)⁽¹⁾
4 MHz
1: This is not compatible with USB operation. The
USB module must be disabled to use this
system clock option.
TABLE 9-3:
VALID PRIMARY OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
Input Oscillator
Frequency
Clock Mode
PLL Division
(PLLDIV<3:0>)
48 MHz
ECPLL
12 (0111)
32 MHz
HSPLL, ECPLL
8 (0110)
24 MHz
HSPLL, ECPLL
6 (0101)
20 MHz
HSPLL, ECPLL
5 (0100)
16 MHz
HSPLL, ECPLL
4 (0011)
12 MHz
HSPLL, ECPLL
3 (0010)
8 MHz
ECPLL, XTPLL,
FRCPLL⁽¹⁾
2 (0001)
4 MHz
ECPLL, XTPLL,
FRCPLL⁽¹⁾
1 (0000)
Note 1: This requires the use of the FRC self-tune
feature to maintain required clock accuracy.
FIGURE 9-2:
PLL BLOCK
(Note 1)
Input from
POSC
Input from
FRC
(4 MHz or
8 MHz)
PLLDIV<3:0>
 12
8
6
5
4
3
2
1
0111
0110
0101
0100 4 MHz
0011
0010
0001
0000
96 MHz
PLL
2
32 MHz
3
48 MHz Clock
for USB Module
8
4
11 _{PLL Output}
10 for System Clock
 2 ₀₁
 1 ₀₀
CPDIV<1:0>
Note 1: This MUX is controlled by the COSC<2:0> bits when running from the PLL, or the NOSC<2:0> bits when
preparing to switch to the PLL.
 2012-2013 Microchip Technology Inc.
DS30009312B-page 167