PIC24FJ128GC010 Datasheet, PDF (352/472 Pages) Microchip Technology – 16-Bit Flash Microcontrollers with 12-Bit Pipeline A/D, Sigma-Delta A/D, USB On-The-Go and XLP Technology

PIC24FJ128GC010 FAMILY
REGISTER 26-3: ADCON3: A/D CONTROL REGISTER 3
R/W-0
U-0
U-0
U-0
R/W-0, HC
ADRC⁽¹⁾
—
—
—
SLEN3
bit 15
R/W-0, HC
SLEN2
R/W-0, HC
SLEN1
R/W-0, HC
SLEN0
bit 8
R/W-0
ADCS7⁽²⁾
bit 7
R/W-0
ADCS6⁽²⁾
R/W-0
ADCS5⁽²⁾
R/W-0
ADCS4⁽²⁾
R/W-0
ADCS3⁽²⁾
R/W-0
ADCS2⁽²⁾
R/W-0
ADCS1⁽²⁾
R/W-0
ADCS0⁽²⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
W = Writable bit
HC = Hardware Clearable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10
bit 9
bit 8
bit 7-0
ADRC: A/D Conversion Clock Source (TSRC) bit⁽¹⁾
1 = Conversion clock derived from FRC (TSRC = TFRC)
0 = Conversion clock derived from system clock (TSRC = TSYS)
Unimplemented: Read as ‘0’
SLEN3: A/D Sample List 3 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL3CONL<12:8> are processed
0 = Sampling for this list is disabled
SLEN2: A/D Sample List 2 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL2CONL<12:8> are processed
0 = Sampling for this list is disabled
SLEN1: A/D Sample List 1 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL1CONL<12:8> are processed
0 = Sampling for this list is disabled
SLEN0: A/D Sample List 0 Enable bit
1 = Sampling for this list is enabled; triggers defined by ADL0CONL<12:8> are processed
0 = Sampling for this list is disabled
ADCS<7:0>: A/D Conversion Clock Prescaler bits⁽²⁾
TAD = TSRC·(2·ADCS<7:0>)
Except When ADCS<7:0> = 00h:
TAD = TSRC
Otherwise:
00100001 and higher = Reserved
00100000 = 32·TSRC
00011111 = 31·TSRC
···
00000010 = 4·TSRC
00000001 = 2·TSRC
Note 1: This bit must be set for Sleep operation.
2: Final A/D clock frequency (1/TAD) must be at or between 1 MHz and 10 MHz.
DS30009312B-page 352
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